Historically, peripheral devices such as input/output (I/O) storage devices and computer networks were connected to the associated computer through a host interface proprietary to that computer. The peripheral devices themselves were standard, each computer model had its own physical connection and data flow protocol to each interface with a peripheral device. Over time, open systems have evolved and standardization has occurred as usage has increased at the workstation and PC levels such that standardized interfaces to the peripherals have become more common.
Over time, the point of interface has changed from being located at the host computer devices themselves to being located in standardized controllers interposed between the devices and the computer. These controllers use a relatively standard interface into the computer system. The forms of standardized bus now integrated into a computer are typically the VME bus, the EISA bus, the NuBus, and the SBus, among others. Such standardized buses work well within a conventional computer architecture in which all processors, memory, and I/O controllers either reside on a common bus, or several tightly coupled busses. In these systems, data accesses are performed as simple indivisible operations which complete relatively quickly within predictable time limits. This type of access is referred to as low latency deterministic access.
The current state of the art is evolving toward parallel distributed systems. These systems are modular and are loosely coupled, so that the processing modules can be geographically separated. Architecturally, these systems are not as tightly coupled and bound as the traditional work station where a bus, a memory, and other components are tied together at a single point. The interconnection between elements of a distributed system is instead more closely associated with a network paradigm than with a bus paradigm.
A network paradigm is characterized by long, indeterminate access latencies, out-of-order completion, and split transactions, wherein a request is sent to multiple memory nodes and some time later a complete response appears. A network configuration does not tie up the system resources for the duration of the access. This differs from a traditional bus paradigm wherein the system sends an address, and waits to get the data transfer to complete the operation. As systems become less bound together, bus architectures become less desirable.
A technological advantage could be gained, both from a performance standpoint and an availability of resources standpoint, by using the existing product base of standardized I/O bus controllers in a network-type distributed memory system. A substantial problem occurs because the standard I/O bus controllers and network type distributed memory systems typically incorporate different memory access protocols. In particular, the I/O controller is a device used in systems that very likely expect and require a low latency "atomic" access, in which an address is sent, and data is received in one indivisible operation, while parallel systems utilize distributed memory arranged with network-type interconnections and characterized by out-of-order completions.
Thus, one problem in the prior art which should be resolved is to incorporate existing standard (bus protocol) I/O controllers, device controllers, or interface controllers into parallel architecture systems.
Another problem is to utilize such bus type devices in a system having long latencies and out-of-order completions.